1. Technical Field
The present invention relates to a semiconductor device with vertical gate having a vertical gate electrode and a method of manufacturing the semiconductor device with vertical gate.
2. Description of the Related Art
With recent requirements for a decrease in power consumption, an improvement in functional performance, and an increase in operation speed in electronic apparatuses, a decrease in power consumption and an increase in operation speed have been also required in semiconductor devices built therein. In order to cope with these requirements, it is necessary to reduce on-resistance of semiconductor devices such as power MOS (Metal Oxide Semiconductor) transistors used in a DC-DC converter or the like of the electronic apparatuses.
Such a type of power semiconductor device employs a vertical-gate structure in which a gate electrode of a semiconductor device is arranged in a direction (hereinafter, referred to as a vertical direction) perpendicular to a principal surface of a semiconductor substrate. For example, in a vertical-gate MOS transistor, a source region on the top of the gate electrode arranged in the vertical direction, a body region in an intermediate portion of the gate electrode, and a drain region on the bottom of the gate electrode are arranged to face each other. In order to further reduce the on-resistance of such a semiconductor device with vertical gate, it is necessary to raise the density of unit cells per unit area.
In the vertical-gate MOS transistor, a source region and a body contact region are formed in the surface of a semiconductor substrate adjacent to the gate electrode. A source electrode electrically connected to the source region and the body contact region is formed on the surface of the semiconductor substrate. An insulating film electrically isolating the gate electrode and the source electrode is formed on the top surface of the gate electrode. In this structure, when the insulating film on the gate electrode protrudes from the surface of the semiconductor substrate and when the vertical gate electrodes are arranged with a small pitch to raise the density of unit cells per unit area, the insulating films get close to each other to form concave portions. These concave portions cause a problem in that voids are formed in the source electrodes embedded in the concave portions, or the like.
As a countermeasure, for example, Unexamined Japanese Patent Publication No. 2005-209807 proposes a technique of forming the top surface of an insulating film on a vertical gate electrode and the surface of a silicon substrate in which a source region exists to form the same plane (including substantially the same plane) in a semiconductor device with vertical gate having plural vertical gate electrodes arranged in parallel. In this technique, the top surface of the vertical gate electrode retreats downward from the surface of the silicon substrate and the source region is then formed on the surface of the silicon substrate. The insulating film is formed on the vertical gate electrode and then a body contact region is formed using a mask patterning (lithography technique). Other examples of such a technique are disclosed in Unexamined Japanese Patent Publication No. 2007-500454 and Japanese Patent No. 4,545,679.